1. Field of the Invention
The present invention relates to a semiconductor memory device such as a floating-gate type non-volatile semiconductor memory device and a read-only memory device.
2. Description of the Prior Art
In a floating-gate type non-volatile semiconductor memory device, a stacked gate structure obtained by stacking a control gate on a floating gate has been examined to decrease a memory cell area and to improve an integration level. FIGS. 1 to 3 show a conventional NOR EPROM which is a kind of a non-volatile semiconductor memory device having such a structure.
In this prior art, an SiO.sub.2 film 12 is formed on the surface in the field region of an Si substrate 11, and first and second polysilicon films 13 and 14 formed on the Si substrate 11 serve as a floating gate and a control gate i.e., a word line, respectively. N.sup.+ -type regions 15 and 16 are formed in active regions on both the sides of the polysilicon films 13 and 14, and the polysilicon films 13 and 14 are covered with an interlayer insulator 17 and a planarizing film 18.
A contact hole 21 reaching the n.sup.+ -type region 15 is formed in the planarizing film 18 and the interlayer insulator 17, and an Al film 22 serving as a bit line is connected to the n.sup.+ -type region 15 through the contact hole 21. Therefore, the n.sup.+ -type region 15 serves as a data output electrode of a memory cell, and the n.sup.+ -type region 16 serves as a ground line.
Although the Al film 22 is formed by sputter deposition, the Al film 22 is originally poor in step coverage. Furthermore, since the contact hole 21 has a large step difference in the stacked gate structure described in this prior art, the step coverage of the Al film 22 is further degraded. For this reason, as shown in FIG. 2, since a size l of the contact hole 21 itself and a size d of each of marginal regions, for planarization, ensured on both the sides of the contact hole 21 cannot be decreased, an integration level cannot be easily improved.
Since the peripheral portion of the contact hole 21 is planarized by a flow or the like as described above, in a lithographic process for patterning the Al film 22, a sharp signal for mask alignment cannot be obtained. For this reason, as shown in FIG. 3, a size o of each of marginal regions, for mask alignment, ensured on both the sides of the contact hole 21 cannot be decreased, and an integration level cannot be easily improved.
In addition, as is apparent from FIG. 1, since the contact holes 21 are adjacent to each other in a direction perpendicular to an extending direction of the Al film 22, an interval s between the Al films 22 is minimum at this position. In addition, as described above, a size l' of the contact hole 21 itself and the size o of each of the marginal regions cannot be decreased. For this reason, an integration level cannot be easily improved in this portion.
As is apparent from FIGS. 1 and 2, there are a large number of contact holes 21 for the Al films 22, i.e., each of the contact holes 21 is formed in memory cells corresponding to two bits. As described above, the Al film 21 is poor in step coverage. For this reason, the above prior art has poor reliability.